1. Field of the Invention
The present invention relates generally to computer systems. More particularly, the present invention relates to fault-tolerant computer systems.
2. Description of the Background Art
Previous solutions for providing fault tolerance in digital processing systems include hardware-based solutions, software-based solutions, or some combination of both.
The hardware schemes require much extra system hardware. The redundant system hardware may be operated, for example in lock-step or utilizing complex voting schemes. The software schemes may be performed either by executing the program multiple times on the same computer or in parallel on multiple computer systems.
Typically, the program is re-run at least three times, resulting in effective execution times that are three times greater than they are without the software verification. As such, the software fault-tolerant solution disadvantageously requires a longer run-time or requires multiple computer systems.
Combination schemes require extra hardware, at least two times, and typically utilize software check-pointing. Software check-pointing involves, upon an error, the capability to re-run a specific instruction sequence.
All the above-discussed solutions are expensive in terms of cost and/or system performance. Hence, improvements in systems and methods for providing fault tolerant digital processing are highly desirable.